Semiconductor and photonics development is R&D-intensive by its nature: device physics, process engineering and packaging each carry uncertainty that published knowledge cannot resolve, and iteration is the working method. South Wales hosts a recognised compound semiconductor cluster, and we work on its doorstep, so these claims are familiar territory for us.
What counts as qualifying R&D in semiconductors and photonics?
Work seeking an advance in the field through uncertainty a competent professional could not readily resolve. At concept level, that regularly includes:
- Device development: new structures, materials systems and geometries where performance cannot be predicted from published results.
- Process development: epitaxy, deposition, etch and lithography work where yield, uniformity or repeatability at target specification is genuinely uncertain.
- Packaging and integration: thermal, optical and electrical behaviour of novel assemblies, including photonic integration.
- Test and characterisation method development where existing techniques cannot measure what the device work requires.
Routine yield improvement within an established process window is the honest boundary: optimisation using known methods does not qualify, while work pushing past what the process can demonstrably do often does. Iteration records, wafer runs and characterisation data make strong evidence, and documentation expectations reward teams that keep them.
Which costs carry these claims?
Staff costs dominate: device engineers, process engineers and test teams, apportioned to qualifying projects. Wafers, materials and consumables used in development runs qualify where they are not sold on, and cloud and software costs for simulation and design tools can qualify too: see the full cost categories. Fabrication facilities (‘fabs’) and equipment purchases are capital and sit outside the credit under separate rules, so the revenue and capital boundary needs setting early.
Which scheme fits?
Fabless and pre-revenue device companies with heavy engineering payrolls are often exactly the ERIS profile: a loss-making SME spending at least 30% of total expenditure on R&D can receive up to 26.97p per £1 of qualifying spend, a £26,970 payable credit on £100,000. Profitable companies claim the merged scheme, worth £15,000 to £16,200 net per £100,000. The PAYE cap has an exemption where the company is creating or managing intellectual property, which IP-rich semiconductor businesses frequently meet. Start with the claim value calculator or which scheme applies.
Sector points worth knowing
- Grant funding, including Innovate UK programmes, no longer blocks or reduces relief under the current schemes: see the current grant position.
- Foundry and shuttle-run arrangements can raise the contracted-out question of who claims which work.
- Overseas fab runs need checking against the overseas restrictions; the exception is narrow and cost alone does not justify it.
Talk it through with a chartered adviser
If your company is developing devices, processes or photonic systems, we will give you a straight view on eligibility and scheme fit. Call 0330 223 4 223 or send us a message.
Written by Matthew Jones ACA CTA. Last reviewed July 2026.